library ieee;
use ieee.std_logic_1164.all;

entity ANDgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end ANDgate;

architecture rtl of ANDgate is
  begin
    C <= A and B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseAND is
port(
  en  : in std_logic;
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseAND;

architecture rtl of bitwiseAND is
signal inA,inB : std_logic_vector(31 downto 0);
  begin
	inA 	<= A and (31 downto 0 => en);
	inB 	<= B and (31 downto 0 => en);
    andReg: for i in 0 to 31 generate
      cellAND: entity work.ANDgate(rtl) port map(inA(i),inB(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity ORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end ORgate;

architecture rtl of ORgate is
  begin
    C <= A or B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseOR is
port(
  en  : in std_logic;
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseOR;

architecture rtl of bitwiseOR is
signal inA,inB : std_logic_vector(31 downto 0);
  begin
	inA 	<= A and (31 downto 0 => en);
	inB 	<= B and (31 downto 0 => en);
    orReg: for i in 0 to 31 generate
      cellOR: entity work.ORgate(rtl) port map(inA(i),inB(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity XORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end XORgate;

architecture rtl of XORgate is
  begin
    C <= A xor B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseXOR is
port(
  en  : in std_logic;
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseXOR;

architecture rtl of bitwiseXOR is
signal inA,inB : std_logic_vector(31 downto 0);
  begin
	inA 	<= A and (31 downto 0 => en);
	inB 	<= B and (31 downto 0 => en);
    xorReg: for i in 0 to 31 generate
      cellXOR: entity work.XORgate(rtl) port map(inA(i),inB(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity NORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end NORgate;

architecture rtl of NORgate is
  begin
    C <= A nor B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseNOR is
port(
  en  : in std_logic;
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseNOR;

architecture rtl of bitwiseNOR is
signal inA,inB : std_logic_vector(31 downto 0);
  begin
	inA 	<= A and (31 downto 0 => en);
	inB 	<= B and (31 downto 0 => en);
    norReg: for i in 0 to 31 generate
      cellNOR: entity work.NORgate(rtl) port map(inA(i),inB(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------